The networking of control units, sensor systems and actuator systems with the aid of a communications system and a communications link such as in the form of a bus system, has increased drastically in recent years in the construction of modern motor vehicles or also in machine construction, especially in the field of machine tools, as well as in automation. In this context, synergistic effects can be achieved by the distribution of functions to a plurality of control units. These are called distributed systems.
Increasingly, the communication between various users of such a data transmission system is taking place via a bus system. Communication traffic on the bus system, access and receiving mechanisms, as well as error handling are regulated by a protocol. One conventional protocol is, for instance, the FlexRay protocol, which is currently based on the FlexRay protocol specification v2.1. FlexRay is a fast, deterministic and error-tolerant bus system, especially for use in motor vehicles. The FlexRay protocol operates according to the principle of time division multiple access (TDMA), in which the users or the messages to be transmitted are assigned fixed time slots during which they have exclusive access to the communications link. The time slots repeat at a fixed cycle, so that the instant at which a message is transmitted via the bus can be predicted exactly, and the bus access takes place deterministically.
To optimally utilize the bandwidth for the message transmission on the bus system, FlexRay subdivides the cycle into a static and a dynamic portion. The fixed time slots are in the static portion at the beginning of a bus cycle. In the dynamic part, the time slots are assigned dynamically. Therein, the exclusive bus access is enabled for a short time only in each case, for the duration of at least one so-called mini slot. The time slot is lengthened by the necessary time only if a bus access takes place within a minislot. Consequently, bandwidth is used up only if it is also actually needed.
In the process, FlexRay communicates via one or two physically separate lines at a data rate of maximally 10 Mbit/sec in each case. Of course, it is also possible to operate FlexRay at lower data rates. The two channels correspond to the physical layer, in particular of the so-called OSI (open system architecture) layer model. They are used chiefly for the redundant and therefore error-tolerant transmission of messages, but can also transmit different messages, which would double the data rate. It is also possible that the signal transmitted via the transmission links results from the difference of signals transmitted via the two links. The physical layer is designed such that it allows an electrical but also an optical transmission of the signal(s) via the link(s) or a transmission in some other manner.
To realize synchronous functions and to optimize the bandwidth by small intervals between two messages, the users in the communications network require a common time base, the so-called global time. For the clock synchronization, synchronization messages are transmitted in the static portion of the cycle, the local clock time of a user being corrected with the aid of a special algorithm according to the FlexRay specification in such a way that all local clocks run in synchronism with a global clock.
In the transmission of data or messages via such a bus system, pulses are distorted because falling (high-to-low) or rising (low-to-high) flanks are delayed to different degrees on the transmission path. If the transmitted pulse is sampled multiple times (for example, n times per bit) in the receiver with the sample clock (the so-called sampling rate) existing there, then the position of the sampling point, i.e., the selection of exactly one of these n sampling values, decides whether the datum is sampled correctly or incorrectly. This is difficult especially when the sampling instant refers to a flank of the signal and also analyzes a plurality of binary data values (bits) of the transmitter relative thereto, over many periods of the sampling clock. In addition to a pulse distortion, the clock frequency deviation between transmitter and receiver also has an effect here. In this context, the signal to be sampled may be preconditioned in order, for example, to filter out short-duration interferences. Such a filter may then be implemented by evaluating a plurality of sampled signals in the time sequence with a majority decision (so-called voting). It has become clear that the rigid specification of the sampling instant without considering the asymmetrical delays on the different transmission paths leads to problems.
The delay between rising and falling edge of a signal is also known as pulse distortion or asymmetrical delay. Asymmetrical delays may have both systematic and stochastic causes. In the FlexRay protocol systematic delays affect only the rising edges, since synchronization is carried out to the falling edges. Stochastic delays have effects both on the rising and on the falling edges, and are caused by noise occurrences or EMC jitter. It may basically be said that the transmission of the signal via the network structure having passive and active network elements, e.g., connection links, transmitters, throttles, communications controllers, transceiver devices or voltage-level converters (so-called transceivers), active stars, etc. lead to the asymmetrical delay since rising and falling signal edges are propagated through the network structure in different manners.
Because of the fixed selection of the sampling instant per bit (for example, at n/2, in the middle of a bit, given n sampling values per bit), both the influence of the asymmetrical distortion as well as the frequency deviation and the additional time discretization by the sampling is a problem and place high demands on the transmission channel. Increasing the edge steepness so as to reduce the asymmetrical delays would indeed be advantageous for the timing, but on the other hand would require technically more sophisticated and thus more expensive components and, in addition, could have an adverse effect on the EMC response of the data transmission system. Therefore, it is sometimes more advantageous not to select the edge steepness to be so great; however, depending on the pulse distortion, one runs the risk of evaluating the wrong datum either at the one or the other bit boundary.
When realizing FlexRay data transmission systems, in particular in the case of complex systems that include a plurality of star couplers and passive networks, it has also been shown that the asymmetrical delay times that occur there are so great that they exceed a time budget specified by the FlexRay protocol. According to the FlexRay protocol, a sample counter is synchronized, i.e., is set back to 1, with the falling BSS (byte start sequence) edge. Sampling is carried out at a counter reading of 5. In an eight-fold oversampling as it is currently provided in FlexRay, three sampling cycles thus remain between the sampling instant (fifth sampling value) and the eighth sampling value, which, given a communications controller cycle of 80 MHz, thus correspond to 12.5 ns in each case and therefore to a time budget of 37.5 ns in total. This time budget is actually provided to compensate for asymmetrical delays due to the difference between the falling and rising edge steepness. However, as may be the case in complex network topologies or network structures, if the asymmetrical delay exceeds the provided time budget, then this leads an incorrect value being determined in a sampling at the fifth sampling cycle (counter reading of the cycle counter at 5), since the particular bit that should have been sampled was already available at an earlier instant due to the asymmetrical delay and is no longer present due to the early edge change. An analogous treatment holds true for an asymmetrical delay retarded in time. A time budget of four sample clocks corresponding to 50 ns is then available. If the time budget is exceeded in a manner advanced or retarded in time, decoding errors result, that is to say, false data are received.
These decoding errors may be detected by suitable error-detection algorithms, so that it is possible to initiate a renewed transmission of the bit or the entire data frame. A cyclic redundancy check (CRC), for example, may be used as error-detection algorithm. However, if the error detection algorithm responds too frequently, there is the disadvantage of the attendant reduced availability of the data transmission system.
In summary, it can be said that the FlexRay protocol makes demands that the physical layer is unable to meet—at least in the case of complex network topologies.
German Patent Application No. 10 2005 037 263 and German Patent Application No. 10 2005 060 903 describe possibilities for reducing the frequency of decoding errors due to an asymmetrical delay of the transmitted signal and for increasing the immunity of the data-transmission system with regard to asymmetrical delays. In both cases a modification on the logical level of the communications controller of the receiving user is proposed. German Patent Application No. DE 10 2005 060 903 suggests, in particular, to measure the asymmetrical delay of the received signal in the communications controller of the receiving user and to sample the bits of the data encoded in the received signal not at a fixed instant but at variable sampling instants, the optimal sampling instant being adjusted as a function of the measured asymmetrical delay. Furthermore, it is suggested in German Patent Application No. DE 10 2005 037 263 to define a sampling range that includes a plurality of sample clocks on the basis of the measured asymmetrical delay prior to the actual sampling, the data bit then no longer being decoded at a single fixed or variable sampling instant. Instead, the decoding of the data bits is implemented taking the values into account that are decoded at the sampling instants in the defined region. Given 8-fold oversampling, this makes it possible to compensate for asymmetrical delays of up to 87.5 ns without the occurrence of decoding faults. Given even higher oversampling, it would even be possible to compensate for correspondingly higher asymmetrical delay times.